The handheld consumer products market is aggressive in the miniaturization of portable electronics. Driven primarily by the cellular phone and digital assistant markets, manufacturers of these devices are challenged by ever shrinking formats and the demand for more PC-like functionality. This challenge asserts pressure on surface mount component manufacturers to design their products to command the smallest area possible. By doing so, this allows portable electronics designers to incorporate additional functions within a device without increasing the overall product size.
In Chip Scale Packaging (CSP) technologies, manufacturers strive to bring the package size as close as possible to the size of the semiconductor chip. The electronics industry has accepted the Joint Electronic Device Engineering Council (JEDEC) defined Quad Flat Pack No Lead (QFN) outlines as good alternatives for low cost chip scale packages. In typical QFN packages, the lower side of a semiconductor chip is attached to a metal lead die attach paddle. Wire bonds are then used to connect circuitry located on the front side of the chip to leads. The chip and lead frame are covered by an epoxy resin to form an assembled component. The die attach paddle and the leads are then attached to a next level of assembly such as printed circuit board.
FIG. 1 shows a cross-sectional view of a conventional QFN package 10 including lead frame 11. Lead frame 11 comprises a slug, flag or die attach portion 13 for supporting semiconductor chip 14, and leads 16. Wire bonds 17 connect semiconductor chip 14 to leads 16. Epoxy layer 19 covers semiconductor chip 14 and portions of lead frame 11, while leaving lower portions of flag 13 and leads 16 exposed. In the QFN package, leads 16 terminate at the edge of the package to provide a smaller package footprint. QFN packages typically are square with leads 16 present on all four sides of the lower surface of the package. FIG. 1 shows package 10 attached to a printed circuit board 21, which includes attach or bond pads 22. FIGS. 2 and 3 are isometric top and bottom views respectively of package 10. As shown in FIG. 3, slug 13 and leads 16 are both exposed on the bottom or lower surface of package 10 for attaching to printed circuit board 21.
There are several advantages to QFN packages including small package footprints, matrix lead frame arrays that allow for easier assembly, and established automated assembly tools. However, there are several problems associated with these packages including poor heat transfer capability for high power device applications. Specifically, in device 10 slug 13 is placed next to or adjacent printed circuit board 21, which must accommodate for heat dissipation. This results in inefficient heat dissipation and heat transfer problems, which impact device performance, reliability, and product life span.
Accordingly, a need exists for a package structure and method of assembly that provide enhanced heat dissipation capability. It is desirable for such a structure and method of assembly to be cost effective by using, for example, existing assembly process techniques.